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WILSONVILLE, Ore., Nov. 6 -- Mentor Graphics Corp. (Nasdaq: MENT), the market and technology leader for hardware/software co-verification, today announced availability of co-verification models to support the development of applications based on the new Xilinx® (Nasdaq: XLNX) Platform FPGA initiative.

The initiative was announced today at a Xilinx press conference and outlines the programmable logic vision for the industry that requires a collaboration among high-level EDA tools, such as Mentor's Co-Verification Environment, embedded processors, Digital Signal Processors (DSPs), and Real Time Operating System technologies using the Xilinx Virtex(TM) architecture. Mentor's contribution to the Xilinx Platform FPGA initiative will include a cycle-accurate processor support package (PSP) of the PowerPC core integrated with Mentor's Seamless® Co-Verification Environment (CVE(TM)).

With rapid advancement in deep-submicron technology, designers can now implement, on an FPGA, system-level functionality that previously could only be deployed on an application specific integrated circuit (ASIC). The introduction of complex embedded processor cores into such devices adds new facets to the design processes not faced in traditional FPGA design. Adding a processor to an FPGA further blurs the traditional distinctions between what functions can go in software and what can go in hardware. The ability to make such tradeoffs throughout the design cycle greatly increases the ability of the design team to reach time to market, as well as performance and feature requirements.

With the Mentor Graphics Seamless CVE, systems-designers and software developers incorporating Xilinx FPGAs based on the Platform FPGA initiative now can validate the fluid hardware/software interfaces in a virtual prototype while both the hardware and software designs are still in progress. The process will help preserve the time-to-market advantage of FPGAs by ensuring early insight into design problems and at the same time enable the hardware and software design flexibility inherent in FPGAs and processors. For Xilinx target customers in time-constrained markets, such as communication systems design and wireless telephony infrastructure, maintaining tight design cycles is often the difference between product success and failure.

``As our new generation of Platform FPGA devices achieve widespread adoption as true-ASIC replacements, Mentor's Seamless CVE will be a key design flow tool for ensuring that our customers maintain the time-to-market benefits that are characteristic of FPGAs, while at the same time exploiting the new capabilities of a fluid hardware/software boundary to achieve the ultimate in system performance and functionality,'' said Rich Sevcik, senior vice president of IP, support and software at Xilinx. ``Mentor Graphics is recognized as being at the forefront of co-verification technology in the ASIC space and its technology is easily modified for the large-FPGA space given our devices' similarity to existing system-on-chip architectures.''

The Xilinx Platform FPGA PSP is based on Mentor's existing general-purpose cycle-accurate co-verification model of the PowerPC core that is already in widespread use. The PSP is tailored to the specific architecture of the Virtex-II implementation of the PowerPC core, simplifying adoption by Xilinx customers. The PSP is integrated with Mentor's XRAY® high-level multi-core debugger and works with all popular logic simulation platforms, including Model Technology's ModelSim® simulation product.

``Our work with Xilinx on their new generation of FPGA extends our co-verification technology into the exploding multi-million gate, system-level FPGA market,'' said Serge Leef, general manager of Mentor Graphics' System-on-Chip Verification division. ``As FPGA designers embed more functionality onto a reprogrammable platform, co-verification becomes as important as it is in System-on-Chip designs implemented in ASICs. Seamless is the best-in-class, market leading co-verification tool capable of verifying not only hard/soft cores but also external interfaces to off-chip processors and high-speed I/O's, key differentiators for this new breed of FPGA.''

Pricing and Availability

The Mentor Graphics Seamless CVE PSP for IBM's PowerPC core is available now on HP and Sun workstations. For more information, including pricing, or to register for a free Seamless workshop, visit our Web site at www.mentor.com/seamless.

About Mentor Graphics Seamless CVE

Combining the best in embedded software development tools with logic simulation, Mentor 's Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $525 million and employs approximately 2,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777. Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

NOTE: Mentor Graphics, XRAY, Seamless and Modelsim are registered trademarks of Mentor Graphics Corporation. Co-Verification Environment (CVE) is a trademark of Mentor Graphics Corporation. PowerPC is a trademark of IBM. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.. All other company or product names are the registered trademarks or trademarks of their respective owners.

CONTACT: Wendy Slocum of Mentor Graphics Corporation, 503-685-1145, or wendy_slocum@mentor.com; or Jeremiah L. Glodoveza of Benjamin Group/BSMG Worldwide, 415-352-2628, or jeremiah@benjamingroup.com, for Mentor Graphics Corporation.